Important characteristics of any data storage cell include the read/write times of the cell, or the time that it takes to read data out of and write data into the cell. While it is desirable to optimize, i.e. shorten, these read/write cycles or times, it is also important that the cell be capable of stably storing data. That is, the cell must be capable of storing data so that it is not disturbed during a selected read or write operation.
One well known circuit arrangement for a binary storage cell is the bistable latch, typically comprised of a pair of cross-coupled bipolar transistors connected in a bistable configuration. At any given time, the two transistors are alternatingly conducting and non-conducting, the particular transistor status determining the value of the stored binary data. Many different configurations of such bistable latches are known, each providing particular advantages and disadvantages.
The following publications show examples of data storage cells including cross-coupled bipolar transistors connected in a bistable latch arrangement: U.S. Pat. No. 3,421,026 to Stopper; IBM Technical Disclosure Bulletin, titled: "Memory Cell Using Schottky Collector Vertical PNP Transistors", Vol. 22, No. 1, June 1979; and IBM Technical Disclosure Bulletin, titled: "Static RAM Cell With Selected Barrier Height Schottky Diodes", Vol. 24, No. 1A, June 1981.
In prior art memory cells comprised of cross-coupled, bistable transistor pairs, a trade-off is typically encountered between speed and reliability. Memory cells of the type wherein the bistable latch transistors are maintained in a non-saturated state are typically fast, such cells avoiding the relatively longer times necessary to switch the transistors into and out of the saturation state. However, such memory cells are more prone to disturbance than is desirable, particularly during read/write operations.
The following publications show memory cells wherein cross-coupled bipolar transistors are operated in the non-saturation mode as bistable latches: U.S. Pat. No. 4,090,255 to Berger et al. (assigned to the assignee of the present invention); U.S. Pat. No. 3,979,735 to Payne; and U.S. Pat. No. 4,070,656 to Heuber et al. (assigned to the assignee of the present invention).
Memory cells of the type wherein the bistable latch transistors are operated in the saturation mode are typically more reliable than those operated in the non-saturation mode. These memory cells, however, often suffer from slow read and write times necessitated by the switching of the transistors into and out of the saturation state.
In addition to optimizing the speed versus reliability characteristics discussed above, further desirable in the operation of a memory cell is the ability to read and write that cell, i.e. a single bistable transistor pair, via a number of different "ports", or read/write address and data lines. Such a capability permits a memory array utilizing such cells to quickly and efficiently select multiple cells for parallel read/write operations.
The following publications show multiple port semiconductor memory devices: U.S. Pat. No. 4,412,312 to Berger et al. (assigned to the assignee of the present invention); U.S. Pat. No. 4,280,197 to Schlig (assigned to the assignee of the present invention); IBM Technical Disclosure Bulletin, titled: "Multi-Port RAM Cell Structure", Vol. 26, No. 7B, December 1983; U.S. Pat. No. 4,415,991 to Chu et al.; IBM Technical Disclosure Bulletin, titled: "Multi-Access Memory Cell", Vol. 27, No. 6, November 1984; and U.S. Pat. No. 4,127,899 to Dachtera (assigned to the assignee of the present invention).